With the advancement of IC integration technology, analog circuits have been incorporated into digital IC's thereby increasing the functions provided by the IC's. An IC with both analog and digital circuits is referred to as "mixed-mode" IC. The analog circuits of the IC often need "clean" power supplies to provide critical circuit performance. Unfortunately, the high-speed switching operation of the logic transitions in the digital circuits of the IC often introduces transient noise on the low (VSS) and high (VDD) voltage power supply busses. This noise generated by the digital circuits can cause the analog circuits of the IC to malfunction or to function with degraded performance. To overcome the noise issue, separate, mutually isolated power supply busses are provided for the analog and digital circuits in mixed-mode IC's. By using separate power supplies and busses for the analog and digital circuits, the noise-coupling effect through the power supply busses is greatly reduced. However, the separated power supply busses cause a new ESD failure as described below.
There are three ESD failure scenarios used to test IC architectures. The schematic circuit diagrams showing the three ESD scenarios are illustrated in FIG. 1, FIG. 2, and FIG. 3. The scenario of FIG. 1 has four of ESD stress modes on IC pins for which testing may be performed. In each mode, a positive or negative ESD voltage applied to a pin with either the VSS pin or the VDD pin grounded. In the ESD-stress scenario of FIG. 1, the ESD protection design for the input or output pins must accommodate the ESD current discharging path of the four modes of ESD stresses. The prior art has proposed numerous suitable ESD protection architectures for protection against the ESD scenario of FIG. 1 for ordinary digital IC's.
FIG. 2 shows a different ESD stress scenario. The positive or negative ESD voltages are applied to an input or output pin with the other input and output pins grounded, and the VDD and VSS pins left floating. This "pin-to-pin" ESD test scenario often causes some unexpected ESD damage to the internal circuits beyond the input or output ESD protection circuits (provided to protect against the scenario shown in FIG. 1).
In the scenario shown in FIG. 3, the ESD voltages are applied directly across the VDD and VSS pins of an IC. Thus, this scenario tests the IC's resistance to VDD-to-VSS ESD stresses. In the VDD-to-VSS ESD test scenario, the positive or negative ESD voltages are applied to the VDD pin with the VSS pin relatively grounded, and with all the input and output pins left floating. This VDD-to-VSS ESD test scenario often causes some unexpected ESD damage to the internal circuits beyond the input or output ESD protection circuits.
To protect the CMOS IC's against the ESD stresses shown in the scenarios of FIGS. 2 and 3, additional ESD protection circuits are generally added to the input and output pins. Specifically, to avoid the unexpected ESD damage to the internal circuits beyond the ESD protection circuits, an additional ESD clamp device is added between the VDD and VSS power supply busses of the IC's. A typical ESD clamp device in the CMOS IC's is the gate-grounded NMOS device. The operation principle of the ESD clamp device between the VDD and VSS power lines in the pin-to-pin ESD stress condition is illustrated in FIG. 4.
As shown in FIG. 4, a positive ESD voltage is applied to an input pin (and therefore to input pad 12) with an output pin (and therefore output pad 14) relatively grounded. The VDD and VSS pads 16 and 18 are left floating. As a result of being allowed to float, the ESD current is first transferred into the floating VDD power supply bus 20 through the diode Dp1 of the input ESD protection circuit 24. Because the output pad 14 is grounded, the floating VSS power supply bus 22 is biased at a voltage level near ground through the parasitic diode Dn2 in the NMOS FET 25 of the output buffer/driver 23. The ESD voltage across the VDD and VSS power supply busses 20, 22 may cause ESD energy (current/voltage) to discharge through the internal circuits 28 of the IC. Because the devices in the internal circuits 28 are often designed and drawn with the minimum device dimension to conserve silicon area of the IC, such ESD energy can damage the internal circuits 28. To protect against this ESD stress, the VDD-to-VSS ESD clamp device 26 is added between the VDD and VSS power supply busses 20, 22. In FIG. 4, the ESD protection clamp 26 is in the form of a gate-grounded NMOS FET connected between the VDD and VSS power supply busses 20, 22. When the ESD stress, due to the pin-to-pin ESD stress of FIG. 2 or the direct VDD-to-VSS ESD stress of FIG. 3, is applied across the VDD and VSS power supply busses 20, 22, the gate-grounded NMOS FET 26 breaks down to clamp the ESD voltage across the power supply busses 20, 22 and to bypass the ESD current away from the internal circuits 28. The dashed lines in FIG. 4 show the ESD current discharging. Therefore, the digital internal circuits of a digital only IC can be protected against the ESD stress.
Consider now the above-described ESD protection architecture in a mixed-mode IC. FIG. 5 illustrates the pin-to-pin ESD stress induced failure in a mixed-mode IC. As before, high voltage VDD and low voltage VSS power supply busses 42, 44 are connected to a digital internal circuit 46. However, separate high voltage VDDA and low voltage VSSA power supply busses 38, 40 are connected to an analog internal circuit 34. The VDD and VDDA busses 42 and 38 are mutually isolated from each other and the VSS and VSSA busses 44 and 40 are mutually isolated from each other. Analog and digital interface circuits (inverters) 48 and 50 enable transfer of a signal from the analog internal circuit 34 to the digital internal circuit 46 yet isolate the two internal circuits 34 and 46 so that noise does not couple between the internal circuits 34 and 46. Diodes Dn1 and Dp1 form an ESD protection circuit 24 for the VDD and VSS busses 42 and 44. Diodes Dp2 and Dn2 form an ESD protection circuit 24' for the VDD and VSSA busses 38 and 40.
In FIG. 5, a positive ESD voltage is applied to an input pad 32 of the analog internal circuit 34 while a digital input pad 36 is relatively grounded and both the analog and digital power supply busses VDDA, VSSA, VDD, VSS 38, 40, 42 and 44 are left floating. Because the digital input pad 36 is grounded, the p-substrate of the mixed-mode IC is initially biased at a voltage level near ground through the diode Dn1. The p-substrate is common for both the digital and analog internal circuits 34 and 46 in a mixed-mode IC. As such, the VSSA power supply bus 40 is also biased at a voltage level near ground through the substrate resistor Rsub. A positive ESD voltage applied to the analog input pad 36 is coupled to the floating VDDA power supply bus 38 by the diode Dp2 in the analog input ESD protection circuit 24'. Because the VSSA power supply bus 40 initially is biased at a low voltage level, the gate of PMOS FET Mp3 of interface circuit 48 is biased at a low voltage level through a parasitic diode Dn4 in the analog internal circuit 34. The ESD charged VDDA power supply bus 38 biases the analog inverter 48 and causes PMOS FET Mp3 to turn on. As a result, the ESD current of the VDDA power supply bus 38 is diverted through Mp3 to the node B between the digital and analog inverters 50 and 48.
Because the digital input pad 36 is grounded, the VDD power supply bus 42 is also initially biased at a low voltage level through the diode Dp1 in the digital input ESD protection circuit 24. The ESD voltage applied to the node B, and the near ground voltages applied to the digital VDD and VSS power supply busses 42 and 44 induce an ESD stress across the gate oxides of the digital inverter 50. This causes the ESD failure to occur at the digital-analog interface circuits 48 and 50. Such ESD failures located at the digital-analog interface circuits 48 and 50 are difficult to identify and can not be observed by only inspecting the leakage current on either the digital and analog input pads 32 and 36 or the VDD, VSS, VDDA or VSSA power supply busses 38, 40, 42 or 44. In other words, full IC function testing, especially testing of the interface functions between the analog and digital circuits 34 and 46, must be performed to locate such an ESD failure. As such, more complex testing technologies must be used in order to detect such ESD damage of the analog-digital interface circuits 48 and 50.
FIG. 6 shows a similar scenario, where the pin-to-pin ESD stress is a positive ESD voltage applied to the digital input pad 36 with the analog input pad 32 relatively grounded, and all the digital and analog VDD, VSS, VDDA and VSSA power supply busses 38, 40, 42 and 44 left floating. As a result of grounding the analog input pad 32, the analog VDDA and VSSA power supply busses 38 and 40 are biased at a voltage level near ground through the diodes Dp2 and Dn2 in the analog input ESD protection circuit 24'. The positive ESD voltage applied to the digital input pad 36 is coupled to the digital VDD power supply bus 42 through the diode Dp1 in the digital input ESD protection circuit 24. Because the VSSA power supply bus 40 is connected to the p-substrate of the mixed-mode IC, the VSS power supply bus 44 is biased at a low voltage level near ground through the substrate resistor Rsub. The VSS power supply bus 44 biases the gate of the PMOS FET Mp1 in the digital inverter 50 through a parasitic diode Dn6 of the digital internal circuit 46. Because the VDD power supply bus 42 is charged by the ESD energy to a positive voltage level, the PMOS FET Mp1 turns on and conducts the ESD current to the node A on the interface line between the digital and analog interface circuits 48 and 50. An ESD voltage is thus applied between node A and the VDDA and VSSA power supply busses 38, 40, i.e, across the gate oxides of the PMOS FET Mp3 and the NMOS FET Mn3 of the inverter 48. As a result, the gate oxides of the PMOS FET Mp3 and NMOS FET Mn3 in the analog inverter 48 may be damaged by the ESD stress.
In a similar fashion, a VDD-to-VSS ESD stress scenario can also damage the interface circuits 48 and 50.
FIG. 7 shows a prior art ESD protection architecture for preventing damage to the interface circuits of a mixed mode IC. In FIG. 7, ESD protection circuits 54, 56 and 58 are added to protect the interface inverters 48 and 50. Specifically, ESD protection circuit 54 includes a PMOS FET Mp4 connected between the interface line 52 and the VDDA power supply bus 38. The gate of the PMOS FET Mp4 is connected to the VDDA power supply bus 38. Likewise, an NMOS FET Mn4 is a connected between the interface line 52 and the VSSA power supply bus 40. The gate of the NMOS FET Mn4 is connected to the VSSA power supply bus 40. The ESD protection circuit 56 includes NMOS FET Mn6 connected as an ESD clamp circuit between the VDD and VSS power supply busses 42 and 44. The ESD protection circuit includes the NMOS FET Mn7 connected as an ESD clamp circuit between the VDDA and VSSA power supply busses 38 and 40. In a pin-to-pin or VDD-to-VSS ESD stress scenario, the ESD voltage across the gate oxides of the interface circuits 48 or 50 is clamped by the ESD protection circuit 54. Therefore, the gate oxides of the interface circuits can be protected against the ESD failure. The problem with the architecture shown in FIG. 7 is that the number of interface lines 52 and interfaces 50 and 48 may be great. Furthermore, the interface lines 52 may be connected in a complex fashion, e.g., one analog interface 48 may be connected to many digital interfaces 50 or vice versa. As such, the architecture of FIG. 7 may be difficult to realize in complex analog-digital interface architectures.
FIG. 8 shows a second prior art solution for preventing ESD failure at the digital-analog interface circuits 48 and 50. In the architecture of FIG. 8, an ESD protection circuit 60 is provided instead of the ESD protection circuit 54. The ESD protection circuit 60 includes an NMOS FET Mn8 connected between opposite polarity VDD and VSSA power supply busses 42 and 40 and an NMOS FET Mn9 connected between opposite polarity VDDA and VSS power supply busses 38 and 44. The gate of Mn8 is connected to the VSSA power supply bus 40 and the gate of Mn9 is connected to the VSS power supply bus 44. If an ESD voltage is applied across the VDD and VSSA power supply busses 42 and 40, the ESD voltage is clamped by Mn8. Likewise, if an ESD voltage is applied across the VDDA and VSS power supply busses and 44, the ESD voltage is clamped by Mn9. Such an architecture does reduce the likelihood of ESD failures at the digital-analog interface circuits 48 and 50. To provide effective ESD protection between the power supply busses 38-44, the NMOS FETs Mn8 and Mn9 are often drawn with large dimensions and the power supply busses 38-44 connected to Mn8 and Mn9 must be made wider in order to quickly bypass the large ESD-transient current. This is undesirable because a large amount of precious IC area must be allocated to ESD protection.
It is an object of the present invention to overcome the disadvantages of the prior art.